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>openocd -f interface/openocd-usb.cfg -f target/lpc2220.cfg -c init -c "flash_boop boop_rom.bin"
Open On-Chip Debugger 0.5.0-dev-00101-gcc197c8-dirty (2010-04-21-22:16)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.berlios.de/doc/doxygen/bugs.html
1000 kHz
adapter_nsrst_delay: 50
jtag_ntrst_delay: 50
trst_and_srst srst_pulls_trst srst_gates_jtag trst_push_pull srst_push_pull
1000 kHz
dcc downloads are enabled
fast memory access is enabled
Info : device: 4 "2232C"
Info : deviceID: 67330064
Info : SerialNumber: A
Info : Description: Dual RS232 A
Info : clock speed 1000 kHz
Info : JTAG tap: lpc2220.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)
Info : Embedded ICE version 4
Info : lpc2220.cpu: hardware has 2 breakpoint/watchpoint units
1000 kHz
Info : JTAG tap: lpc2220.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)
Warn : srst pulls trst - can not reset into halted mode. Issuing halt after reset.
target state: halted
target halted in ARM state due to debug-request, current mode: Abort
cpsr: 0x40000097 pc: 0x00000038
Info : Flash Manufacturer/Device: 0x007f 0x225b
erased sectors 0 through 18 on flash bank 0 in 4.484375s
wrote 239340 bytes from file boop_rom.bin to flash bank 0 at offset 0x00000000 in 4.296875s (54.395 kb/s)
1000 kHz
Info : TAP lpc2220.cpu does not have IDCODE
Warn : JTAG tap: lpc2220.cpu UNEXPECTED: 0x00000000 (mfg: 0x000, part: 0x0000, ver: 0x0)
Error: JTAG tap: lpc2220.cpu expected 1 of 1: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)
Warn : Unexpected idcode after end of chain: 1 0x00000000
Warn : Unexpected idcode after end of chain: 33 0x00000000
Warn : Unexpected idcode after end of chain: 65 0x00000000
Warn : Unexpected idcode after end of chain: 97 0x00000000
Warn : Unexpected idcode after end of chain: 129 0x00000000
Warn : Unexpected idcode after end of chain: 161 0x3c3c0000
Warn : Unexpected idcode after end of chain: 193 0x80013c7c
Warn : Unexpected idcode after end of chain: 225 0x8000007f
Warn : Unexpected idcode after end of chain: 257 0x8000007f
Warn : Unexpected idcode after end of chain: 481 0x00001fff
Warn : Unexpected idcode after end of chain: 513 0x00000000
Warn : Unexpected idcode after end of chain: 545 0x00000000
Warn : Unexpected idcode after end of chain: 577 0x00000000
Error: double-check your JTAG setup (interface, speed, missing TAPs, ...)
error: -100
Command handler execution failed
openocd -f interface/openocd-usb.cfg -f target/lpc2220.cfg -c init
Open On-Chip Debugger 0.5.0-dev-00101-gcc197c8-dirty (2010-04-21-22:16)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.berlios.de/doc/doxygen/bugs.html
1000 kHz
adapter_nsrst_delay: 50
jtag_ntrst_delay: 50
trst_and_srst srst_pulls_trst srst_gates_jtag trst_push_pull srst_push_pull
1000 kHz
dcc downloads are enabled
fast memory access is enabled
Info : device: 4 "2232C"
Info : deviceID: 67330064
Info : SerialNumber: A
Info : Description: Dual RS232 A
Info : clock speed 1000 kHz
Error: JTAG scan chain interrogation failed: all zeroes
Error: Check JTAG interface, timings, target power, etc.
Error: JTAG scan chain interrogation failed: all zeroes
Error: Check JTAG interface, timings, target power, etc.
Command handler execution failed
Warn : jtag initialization failed; try 'jtag init' again.
#
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME lpc2220
}
if { [info exists ENDIAN] } {
set _ENDIAN $ENDIAN
} else {
set _ENDIAN little
}
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x4f1f0f0f
}
#coonfigure reset options
jtag_nsrst_delay 200
jtag_ntrst_delay 200
#use combined on interfaces or targets that can't set TRST/SRST separately
reset_config trst_and_srst srst_pulls_trst
#trst_push_pull srst_push_pull
#jtag scan chain
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
$_TARGETNAME configure -event reset-init {
# setup PLL
# PLLCON: Enable PLL, connect PLL
mww 0xe01fc080 0x03
# VBPDIV: no division
mww 0xe01fc100 0x0
# PLLCFG: 0x42 = psel = 10 (4) = msel= 00010 (3) = 240 mhz Fcco*/
mww 0xe01fc084 0x45
# Activate PLL settings
mww 0xe01fc08c 0xaa
mww 0xe01fc08c 0x55
sleep 20
# Memory Bank Configuration
# BCFG0: 16bit, rble, 6wst - 60 mhz : Betty: FLASH 0 @ 0x80000000
mww 0xffe00000 0x100004A0
# BCFG2: 16bit, rble, 6wst - 60 mhz : Betty: FLASH 1 @ 0x82000000
mww 0xffe00008 0x100004A0
# BCFG1: 8 bit, 3 sram wst, rble, 5 wst 3 idcy : Betty: LCD @ 0x81000000
#mww 0xffe00004 0x00000C42
# GPIO Pin COnfiguration for Flash access
# PINSEL0:
mww 0xe002c000 0x00008005
# PINSEL1:
mww 0xe002c004 0x00000000
# PINSEL2:
mww 0xe002c014 0x0de049d4
# IO2SET: Set Outputs
mww 0xe0028024 0x1FC0000
# IO2DIR: Set Direction
mww 0xe0028028 0x1FC0000
# IO0DIR:
mww 0xe0028008 0x002018D0
# disable watchdog
#mww 0xfffffd44 0x00008000
# enable user reset
#mww 0xfffffd08 0xa5000001
sleep 100
arm7_9 fast_memory_access enable
}
arm7_9 dcc_downloads enable
$_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
#flash bank <name> <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cfi 0x80000000 0x00100000 2 2 $_TARGETNAME
flash bank $_FLASHNAME cfi 0x82000000 0x00100000 2 2 $_TARGETNAME
# For more information about the configuration files, take a look at:
# openocd.texi